There have been recently dramatic increases in the performance of integrated circuit graphic systems, resulting in the requirement for ever increasing data rates. Data rates in mainstream graphics workstations have increased from 25MHz to over 100MHz, and future increases are probable.
Currently, information destined for screen output is stored in a block of memory called a frame store which periodically outputs its information in a serial fashion at a rate called the pixel dot rate. This serial information can be manipulated by graphics hardware at the pixel dot rate and is ultimately converted by a digital-to-analogue converter (DAC) to analogue voltages which can control the electron guns in a cathode ray tube (CRT).
To utilise readily available and cheap memory technology which cannot operate at such high speeds, the aforementioned frame store is split up into a plurality of smaller frame stores which operate more slowly and in parallel. Pixel data from the frame stores is outputted in parallel streams down a pipeline. These pixel streams are combined by a multiplexor into one high speed serial stream, upstream of the DAC.
Generally such combination involves a high speed clock to control this multiplexor. Any graphics hardware required to operate on the high speed serial pixel stream will also have to be controlled by this high speed clock. It is known to provide the multiplexor combining the multiple pixel stream on the same silicon chip as a high speed sequential graphics device even though an external high speed clock at the pixel dot rate frequency has also had to be supplied to control both, This produces a synchronisation problem which is difficult to solve, because the low rate data entering the graphics device is not correlated with the high speed clock. Even if the low rate data is controlled by a signal derived from the high speed clock, for example by using a frequency divider, delays are such that at these high frequencies this has to be viewed as uncorrelated. In addition to this problem extra costs are incurred to generate the high speed clock.
More generally, it is often required to take into a silicon chip several data streams at lower frequencies. Once combined into a single stream this data can be used as the input to another part of the chip. Both stages require the input of an external clock which is at the highest frequency that occurs on the chip. This is expensive and produces synchronisation problems.
It is an object of the present invention to solve the problem of synchronising incoming data at a low rate with an integrated circuit processing device utilising that data at a higher rate.